1. Field of the Invention
The present invention relates to an ethernet protocol, and more particularly, to an address detecting device of an ethernet controller and an address detecting method thereof suitable for detection of a packet address input from network interface card (NIC) connected to local area network (LAN).
2. Discussion of the Related Art
Generally, the use of local area network (LAN) for interconnecting data terminal equipments (DTEs), such as computers, word processors or the like, is well-known. In the LAN, each of devices has its inherent address and a plurality of group addresses. A network interface card is mounted in each one of the DTEs and couples each one of the DTEs to a transmission media. Each of the DTEs compares an address transmitted to the network interface card with a group address as well as its inherent address. As a result, each of the DTEs receives data or does not receive data. The data transmission and reception between each of the DTEs on the network are performed in packet units.
Therefore, each of the DTEs detects a destination address of data input in packet units. The DTE receives a current transmission packet if the detected destination address corresponds to its destination address. While the DTE does not receive a current transmission packet if the destination address does not correspond.
A conventional address detecting device of an ethernet controller will be described with reference to FIG. 1.
FIG. 1 is a schematic block of a conventional address detecting device of an ethernet controller.
As illustrated in FIG. 1, the conventional address detecting device includes a system bus interface 13, a media access controller (MAC) 15, and an attachment module 17.
The system bus interface 13 is connected to a system bus 11. The attachment module 17 receives packet data from each of the network. The attachment module 17 which is called a front end module performs modulation and demodulation functions for receiving data from the network and transmitting data to the network.
As illustrated in FIG. 2, the MAC 15 includes an SRAM 15a, a first-in first-out (FIFO) memory 15b, and a comparator 15c.
The comparator 15c is connected to the SRAM 15a and the FIFO memory 15b. The SRAM 15a stores a plurality of group addresses. The FIFO memory 15b receives a destination address of transmission data in packet unit and outputs it to the comparator 15c. The comparator 15c compares the group address stored in the SRAM 15a with the destination address output from the FIFO memory 15b.
The system bus interface 13 is disposed between the system bus 11 and the MAC 15.
A conventional address detecting method of the aforementioned conventional address detecting device of the ethernet controller will be described below.
As illustrated in FIG. 1 and FIG. 2, the destination address is input to the FIFO memory 15b of the MAC 15 and output to the comparator 15c.
At this time, a plurality of group addresses are stored in the SRAM 15a. The comparator 15c compares the group addresses stored in the SRAM 15a with the address output from the FIFO memory 15b. As a result, if the addresses stored in the SRAM 15a are coincident with the address output from the FIFO memory 15b, a hit signal which is indicative of the coincidence is output by the comparator. If not, the data stored in the FIFO memory 15b and the SRAM 15a are reset.
In the address detecting method according to the address detecting device of FIG. 1, the address detecting block is disposed within the MAC 15.
Another conventional address detecting device in which the address detecting block is disposed outside from the MAC 15 will now be described.
As illustrated in FIG. 3, another conventional address detecting device includes a system bus interface 13, an MAC 15, an attachment module 17, and an address detector 19.
The address detector 19 is connected to the MAC 15 and the attachment module 17, respectively.
The system bus interface 13 is disposed between the system bus 11 and the MAC 15.
The address detector 19 compares the group address stored in the MAC 15 with the destination address output from the attachment module 17 to detect whether these addresses are coincident with each other. In the MAC 15, the SRAM (not shown) is mounted to store the group address.
In the aforementioned conventional address detecting device, the address detecting block disposed outside of the MAC 15 compares the group address stored in the MAC 15 with the address output from the attachment module 17 and transmits the comparative result to the MAC 15.
A conventional address detecting method according to a software hash method will now be described.
The software hash method performs a polynomial CRC algorithm. An 8 byte multicast table is prepared based on the result of such a CRC algorithm.
FIG. 4 shows the CRC algorithm.
As illustrated in FIG. 4, a bit is set in a position of multicast address register defined by the CRC algorithm. By doing so, the multicast table is prepared.
FIG. 5 shows the prepared multicast table.
If the packet is input to the address detecting block after preparing the multicast table, the CRC algorithm for the packet is performed. It is then determined whether a bit is set in a corresponding position referring to the multicast table by the result of such algorithm. If so, the address detecting device receives the packet. If not, the address detecting device does not receive the packet.
The conventional address detecting device of the ethernet controller and the conventional address detecting method thereof have several problems.
First, since the software hash method has an extremely low speed, and the processing ability of the packet is remarkably reduced.
In addition, the method for detecting the address within the MAC requires many storage regions to store all of group addresses. It also reduces processing ability of the packet because all group addresses are compared until the addresses are coincident whenever the packet is received.